Implementing MIPI DSI-2 on an Agilex 5 device

I updated the parameters on the Video Timing tab changing only to these values: Htotal = 1751 and Hbend = 1623

I re-ran the simulation and this time, I see a fatal "CRC value is wrong" error instead of the original back pressure issue.

# dsi2_ed_sim_tb.test_inst: STARTING TEST!
# dsi2_ed_sim_tb.test_inst: Running test with 10 frames
# dsi2_ed_sim_tb.test_inst: Using VVP Image Information Config: '{}
# dsi2_ed_sim_tb.test_inst: Line Packet Length = 384 Bytes;
# dsi2_ed_sim_tb.test_inst:
# dsi2_ed_sim_tb.test_inst.run_test: Loading Tasklist to execute!
# dsi2_ed_sim_tb.test_inst.run_test: Estimated Tasklist size: 3860
# dsi2_ed_sim_tb.test_inst.run_test: Finished loading Tasklist!
# dsi2_ed_sim_tb.test_inst.run_test: This Tasklist contains: 991 tasks to execute!
# dsi2_ed_sim_tb.test_inst.run_test:
# dsi2_ed_sim_tb.test_inst.axis_source: Sending VVP Image Information Packet: 67005f007f0240
# ** Fatal: CRC value is wrong
# Time: 179030 ns Started: 179023333333 fs Scope: dsi2_ed_sim_tb.dut.dsi2_tx.dsi2_tx.dsi2.mipi_dsi2_tx_inst.<protected>.<protected>.<protected> File: ../../../rtl/ip/dsi2_dphy_sys/dsi2_dphy_sys_dsi2_tx/intel_mipi_dsi2_core_100/sim/intelfpga/mipi_dsi2_tx_packetizer.sv Line: 130
# ** Note: $finish : ../../../rtl/ip/dsi2_dphy_sys/dsi2_dphy_sys_dsi2_tx/intel_mipi_dsi2_core_100/sim/intelfpga/mipi_dsi2_tx_packetizer.sv(130)
# Time: 179030 ns Iteration: 10 Protected: /dsi2_ed_sim_tb/dut/dsi2_tx/dsi2_tx/dsi2/mipi_dsi2_tx_inst/<protected>/<protected>/<protected>