'Illegal directional connection'error in Quartus 8.0

I don't know what an "Illegal directional connection" exactly is. Is it a compiler or fitter error message?

I would primarly look for the logic definition and possibly defined pin attributes and other specific assignments. I also would try with a newer Quartus version, e.g. a stable 9.0.

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I don't know what an "Illegal directional connection" exactly is. Is it a compiler or fitter error message?

I would primarly look for the logic definition and possibly defined pin attributes and other specific assignments. I also would try with a newer Quartus version, e.g. a stable 9.0.

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In my project,I define a 'INOUT' , and the project is well run in Quartus 5.0.Now I want to compile in Quartus 8.0, during the systhesis it get errors.

Best Regards!

I have defined a 'inout' in top module

data : INOUT std_logic_vector (15 downto 0);

and then I call a component and use the data as bidiretional interface.

port map

(data_in=>data,

data_out=>data,).

I don't know the port type of data_out, but this most likely can't work. You'll need a tristate driver interface.

port map
(data_in=>data,
data_out=>data_o);
data <= data_o when (enable_condition) else (others => 'z');

P.S.: If data_out is of the output type, and you simply want to override the inout character of data (permanently enable the output buffer), there may be technical problem of the Quartus compiler. In this case, try to insert a dummy signal between data_out and data.

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I don't know the port type of data_out, but this most likely can't work. You'll need a tristate driver interface.

port map
(data_in=>data,
data_out=>data_o);
data <= data_o when (enable_condition) else (others => 'z');

P.S.: If data_out is of the output type, and you simply want to override the inout character of data (permanently enable the output buffer), there may be technical problem of the Quartus compiler. In this case, try to insert a dummy signal between data_out and data.

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Thanks a lot!

data_out is defined as 'output', I still confused that my project is no problem during Quartus 5.0 environment.I doubt that the version of Quartus 8.0 don't support some VHDL grammar anymore.

Besides I am not familiar with VHDL, so I'm not sure

port map(

data<= data_o when (enable_condition) else (others=>'z')

)

can be complied without errors or warnings.

Thank you very much!

you cant compile it directly into a port map.

data<= data_o when (enable_condition) else (others=>'z')

data would the the top level I/O, with data_o being a temporary signal inside the architecture.