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Altera_Forum
Honored Contributor
14 years agoBesides I am not familiar with VHDL, so I'm not sure
port map( data<= data_o when (enable_condition) else (others=>'z') ) can be complied without errors or warnings. Thank you very much!Besides I am not familiar with VHDL, so I'm not sure
port map( data<= data_o when (enable_condition) else (others=>'z') ) can be complied without errors or warnings. Thank you very much!