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Altera_Forum's avatar
Altera_Forum
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10 years ago

ID 12006 Undefined entity

Hi just a quick run down of what im trying to achieve write a value to my verilog code and read back the double value (input*2) gonna expand later on...(im new to FPGA)

ive greated a Qsys module as described here:

ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/making_qsys_components.pdf

the plan is the write/read a value from NIOS (hello_world) template to the new component(modified to return 2* input value, and removed the HEX output).

1.) Qsys module created (ok)

2.) Qsys generate HDL (ok)

3.) Nios project (debug via JTAG) (ok)

-c code function returns same value as written 

void MyReadWrite(void)
{
    static int writeval = 22;
    int readval = 0;
    IOWR(REG16_AVALON_INTERFACE_0_BASE,0,writeval);
    readval = IORD(REG16_AVALON_INTERFACE_0_BASE,0);
    printf("\n Reg16 Test WriteVal: %d, ReadBackVal: %d",writeval,readval);
    writeval++;
}

reply in NIOS concole:

Reg16 Test WriteVal: 22, ReadBackVal: 22

(i think i just write/read to memory somewhere without entering the verilog code. i havent compiled the FPGA code(Quartus project to get a .sof file) yet, at least i dont think so not 100% sure of whats include when i launch a debug session from eclipse)

4.) created a Quartus project (ok)

containing the following files:

-nios_setup.qip

-MyReg16_avalon_interface.v

-MyReg.v

-top.v

-platform/alt_pll/alt_pll.qip

top.sdc

5.) when i try to compile the project i get the following error " Id 12006 instance "comb_4" instantiates undefined entity "nios_setup" (Guess i need to add something to my top.v file just dont know how/what t o add.)

my top.v is a from the ADC demo in the design store. 

module top ( 
    input clk,
    input reset,
    input  SW,
    output  LED
);
wire adc_10M_clk;
wire nios_50M_clk;
wire pll_locked;
wire reset_n;
assign reset_n = !reset;
    all_pll    alt_pll_inst (
   .areset ( reset ),
    .inclk0 ( clk ),
    .c0 ( adc_10M_clk ),
    .c1 ( nios_50M_clk),
    .locked ( pll_locked )
    );
    nios_setup (
        .clk_clk                               (nios_50M_clk),   // clk.clk
        .reset_reset_n                         (reset_n),        // reset.reset_n
        .led_io_external_connection_export        (LED),                // led_pio_external_connection.export
        .sw_io_external_connection_export         (SW),                 // switch_pio_external_connection.export
        .modular_adc_0_adc_pll_clock_clk       (adc_10M_clk),    // modular_adc_0_adc_pll_clock.clk
        .modular_adc_0_adc_pll_locked_export   (pll_locked)        // modular_adc_0_adc_pll_locked.export
    );
endmodule

any explanation on how to make this work would be appreciated.

thanks in advance

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I don't know the solution, but please edit your post so that you have your code in code tags. This makes reading it much easier.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Here is the error:

    nios_setup (

    If you look at how you did your pll you have,

    all_pll alt_pll_inst(

    module ----- instance

    your nios_setup declaration is missing either the module name or the instance name
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi code tags added :-) thanks for the heads up.

    ATT: Krasner ive looked in some different demo project (all working fine) and they all share the same syntaks, " nios_setup ( " so i guess thats okay ?

    here is the verilog code: 

    
module reg16_avalon_interface (clock, resetn, writedata, readdata, write, read,
byteenable, chipselect);
// signals for connecting to the Avalon fabric
input clock, resetn, read, write, chipselect;
input  byteenable;
input  writedata;
output  readdata;
// signal for exporting register contents outside of the embedded system
wire  local_byteenable;
wire  to_reg, from_reg;
assign to_reg = writedata;
assign local_byteenable = (chipselect & write) ? byteenable : 2'd0;
reg16 U1 ( .clock(clock), .resetn(resetn), .D(to_reg), .byteenable(local_byteenable), .Q(from_reg) );
assign readdata = from_reg;
endmodule

    For now this one just returns "11" no matter what input. 

    module reg16 (clock, resetn, D, byteenable, Q);
input clock, resetn;
input  byteenable;
input  D;
output reg  Q;
integer bob;
always@(posedge clock)
if (!resetn)
Q <= 16'b0;
else
begin
// Enable writing to each byte separately
//if (byteenable) Q <= D;
//if (byteenable) Q <= D;
Q <= 16'd11;
end
endmodule

    do i need to add Reg16 to my nios_setup ? and how ?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Also when i create a new project in Nios-eclipse based on my new Qsys file (with the Reg16 component), do i need to load anything to the FPGA og is the debug via JTAG taking care of that ?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    If you are asking, Do I need to reload the hardware, yes you will need to resynthesise the hardware and then reload.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    so after a little magic with filenames vs. component names its running fine now (Thanks for helping)... Im using a Avalon slave and using writedata(16 bit) as input to my vhdl block. What is the correct/best way to expand the input to be fx. 5 variables*16bit?. Is it to have 5 avalon_slaves or how is done properly ?