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Altera_Forum
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11 years ago

ID 12006 Undefined entity

Hi just a quick run down of what im trying to achieve write a value to my verilog code and read back the double value (input*2) gonna expand later on...(im new to FPGA) ive greated a Qsys modul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

so after a little magic with filenames vs. component names its running fine now (Thanks for helping)... Im using a Avalon slave and using writedata(16 bit) as input to my vhdl block. What is the correct/best way to expand the input to be fx. 5 variables*16bit?. Is it to have 5 avalon_slaves or how is done properly ?