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Altera_Forum
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11 years ago

ID 12006 Undefined entity

Hi just a quick run down of what im trying to achieve write a value to my verilog code and read back the double value (input*2) gonna expand later on...(im new to FPGA) ive greated a Qsys modul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Also when i create a new project in Nios-eclipse based on my new Qsys file (with the Reg16 component), do i need to load anything to the FPGA og is the debug via JTAG taking care of that ?