ID 12006 Undefined entity

Hi code tags added :-) thanks for the heads up.

ATT: Krasner ive looked in some different demo project (all working fine) and they all share the same syntaks, " nios_setup ( " so i guess thats okay ?

here is the verilog code:

module reg16_avalon_interface (clock, resetn, writedata, readdata, write, read,
byteenable, chipselect);
// signals for connecting to the Avalon fabric
input clock, resetn, read, write, chipselect;
input  byteenable;
input  writedata;
output  readdata;
// signal for exporting register contents outside of the embedded system
wire  local_byteenable;
wire  to_reg, from_reg;
assign to_reg = writedata;
assign local_byteenable = (chipselect & write) ? byteenable : 2'd0;
reg16 U1 ( .clock(clock), .resetn(resetn), .D(to_reg), .byteenable(local_byteenable), .Q(from_reg) );
assign readdata = from_reg;
endmodule

For now this one just returns "11" no matter what input.

module reg16 (clock, resetn, D, byteenable, Q);
input clock, resetn;
input  byteenable;
input  D;
output reg  Q;
integer bob;
always@(posedge clock)
if (!resetn)
Q <= 16'b0;
else
begin
// Enable writing to each byte separately
//if (byteenable) Q <= D;
//if (byteenable) Q <= D;
Q <= 16'd11;
end
endmodule

do i need to add Reg16 to my nios_setup ? and how ?