LEric4
New Contributor
6 years agoI got a question about timing analysis, for the input delay of source synchronous interface
Hi all,
I got a question about timing analysis, for the input delay of source synchronous interface, there are two ways in the manual , one is using external parameter, one is using FPGA requirement.
If use of external input parameters ,my calculation of Max delay is 1 ns, while using FPGA requirement input Max delay is 13 ns, the timing analysis results are completely different when using the above two ways,
My question is, since the two ways to calculate the input delay value is completely different, how does Quartus know which way we use when do timing analysis?
BR,
Eric