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LEric4's avatar
LEric4
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6 years ago

I got a question about timing analysis, for the input delay of source synchronous interface

Hi all, I got a question about timing analysis, for the input delay of source synchronous interface, there are two ways in the manual , one is using external parameter, one is using FPGA requirement...
sstrell's avatar
sstrell
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6 years ago

The calculated values between the two methods should not be so wildly different. What information do you have and what are your calculations?

#iwork4intel

  • LEric4's avatar
    LEric4
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    6 years ago

    hi sstrell ,thanks for your reply. In my design, take the input max delay as example,

    by using the external parameters, input max delay = Board delay -Board clock Skew + Tco = 1ns,

    by using FPGA requirement, input max delay = T -Tsu = 15.626 -2.5 = 13.125ns, CLK_Freq=64M, Tsu=2.5ns.

    So by using different way, the results were very different, Is my calculation way not correct?