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LEric4's avatar
LEric4
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6 years ago

I got a question about timing analysis, for the input delay of source synchronous interface

Hi all, I got a question about timing analysis, for the input delay of source synchronous interface, there are two ways in the manual , one is using external parameter, one is using FPGA requirement...
sstrell's avatar
sstrell
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6 years ago

Where is the tco value coming from? I don't see that in the data you've provided. It looks like you are given tS and tH, so 13.125 ns is correct for input delay max. Input delay min would be 2.5 ns.

#iwork4intel

LEric4's avatar
LEric4
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6 years ago

I can't find the Tco in the ​chip datasheet, so I set it to 0, can I set it to 0?