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LEric4's avatar
LEric4
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6 years ago

I got a question about timing analysis, for the input delay of source synchronous interface

Hi all, I got a question about timing analysis, for the input delay of source synchronous interface, there are two ways in the manual , one is using external parameter, one is using FPGA requirement...
sstrell's avatar
sstrell
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6 years ago

No, you can't set it to 0. You've got tS and tH and the correct calculations. You don't need to worry about the tco of the external device. You only need to use one method to constrain or the other. Just use 13.125 and 2.5 as I mentioned.

#iwork4intel

LEric4's avatar
LEric4
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6 years ago

​thanks