HPS CLK Initialization issue

Question

Hi team,

In our custom board, we use AGFB014R24B1E1V Intel SoC FPGA. When HPS runs FSBL, the HPS CLK does not get initialized. It is stuck waiting for the main and peripheral PLL lock, but the hardware side clock is fine. Please help resolve the problem and give a procedure to configure HPS CLK in Quartus Prime.

Thanks,

Regards,

Veerappan P.

veerappan · Answer

Hi,

I have doubts about the CLK manager status register main pll lock bit. The issue is the mainplllocked bit is not set. The doubt is where the PPM threshold value is programmed in the memory register.

Thanks,

Regards,

Veerappan P.

kianhint_altera · Answer

Hi Veerappan,Sorry for the delay in getting back to you as I was out on emergency last week. Let me check this up and get back to you later.ThanksRegardsKian

kianhint_altera · Answer

Hi Veerappan,Just to confirmIn platform designer , the EOSC clock frequency used is the correct frequency and the settings for both input and output clocks are set accordinglyexample cyclone V (for agilex you should have 1 EOSC clock only)then since you're running on custom board, have you regenerated the spl and also check the bootloader osc clock settings are set correctly?https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2022.07/arch/arm/dts/socfpga_agilex_socdk.dts (do change the file depending on which board you're referencing to. I'm using agilex soc dev kit)May I know where do you find this table from , at which document. Was trying to find this on my endThanksRegardsKian

veerappan · Answer

Hi,You say https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2022.07/arch/arm/dts/socfpga_agilex_socdk.dts (do change the file depending on which board you're referencing to. I'm using agilex soc dev kit)What changes are made in that file?soc {             clocks {                           osc1 {                                         clock-frequency = &lt;25000000&gt;;                            };               };};This clock device tree parameter is enough to add the clock or some other properties are required. We followed the Apollo Agilex 7 SOM board design for our custom board.This image is taken from the i_clk_mgr_clkmgr register map. The Register Address is 0xFFD10000. Thanks,Regards,Veerappan P.

veerappan · Answer

Hi,

I have gone through the U-boot clock initialization C code but there is no device tree parameter given in .dts file used for clock initialization.

u-boot-socfpga/drivers/clk/altera/clk-agilex.c In this file this is the probe function

static int socfpga_clk_probe(struct udevice *dev)
{
struct cm_config *cm_default_cfg = cm_get_default_config();
clk_basic_init(dev, cm_default_cfg);
return 0;
}

cm_get_default_config(); function is used to get clock configuration information from FPGA and if we go through the clk_basic_init(); function. This data which is from FPGA hands-off is used. Then why do we use clock parameters in the device tree?

Thanks,

Regards,

Veerappan P.

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HPS CLK Initialization issue

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