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Veerappan's avatar
Veerappan
Icon for New Contributor rankNew Contributor
1 year ago

HPS CLK Initialization issue

Hi team, In our custom board, we use AGFB014R24B1E1V Intel SoC FPGA. When HPS runs FSBL, the HPS CLK does not get initialized. It is stuck waiting for the main and peripheral PLL lock,...
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KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Once again I do apologize for the delay in getting back. I will try to address the discussion at the other thread

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-to-use-HPS-internal-clock-in-Agilex-7-SOC/m-p/1658943#M29125

Thanks

Regards

Kian