Forum Discussion
New ContributorHPS CLK Initialization issue
New ContributorHi,
You say
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2022.07/arch/arm/dts/socfpga_agilex_socdk.dts (do change the file depending on which board you're referencing to. I'm using agilex soc dev kit)
What changes are made in that file?
soc {
clocks {
osc1 {
clock-frequency = <25000000>;
};
};
};
This clock device tree parameter is enough to add the clock or some other properties are required. We followed the Apollo Agilex 7 SOM board design for our custom board.
This image is taken from the i_clk_mgr_clkmgr register map. The Register Address is 0xFFD10000.
Thanks,
Regards,
Veerappan P.
New ContributorHi,
I have gone through the U-boot clock initialization C code but there is no device tree parameter given in .dts file used for clock initialization.
u-boot-socfpga/drivers/clk/altera/clk-agilex.c In this file this is the probe function
static int socfpga_clk_probe(struct udevice *dev)
{
struct cm_config *cm_default_cfg = cm_get_default_config();
clk_basic_init(dev, cm_default_cfg);
return 0;
}
cm_get_default_config(); function is used to get clock configuration information from FPGA and if we go through the clk_basic_init(); function. This data which is from FPGA hands-off is used. Then why do we use clock parameters in the device tree?
Thanks,
Regards,
Veerappan P.
