Forum Discussion
Veerappan
New Contributor
New ContributorHPS CLK Initialization issue
Hi team, In our custom board, we use AGFB014R24B1E1V Intel SoC FPGA. When HPS runs FSBL, the HPS CLK does not get initialized. It is stuck waiting for the main and peripheral PLL lock,...
VeerappanNew Contributor
New ContributorHi,
I have doubts about the CLK manager status register main pll lock bit. The issue is the mainplllocked bit is not set. The doubt is where the PPM threshold value is programmed in the memory register.
Thanks,
Regards,
Veerappan P.
