Forum Discussion
Veerappan
New Contributor
1 year agoHPS CLK Initialization issue
Hi team, In our custom board, we use AGFB014R24B1E1V Intel SoC FPGA. When HPS runs FSBL, the HPS CLK does not get initialized. It is stuck waiting for the main and peripheral PLL lock,...
KianHinT_altera
Frequent Contributor
1 year ago####
Sorry, I didn't notice my message didnt get through and was stuck in draft state. Just resend out
Thanks
Regards
Kian
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Hi Veerapan,
Apologies, on your question, this KDB might answer your questions even though it is based on Stratix 10, but it is also applicable for Agilex as well
https://www.intel.com/content/www/us/en/support/programmable/articles/000086394.html
As we are using das u-boot and linux kernel , more information can be obtain from their respective sites
https://docs.kernel.org/devicetree/index.html#devicetree-overlays
https://docs.u-boot.org/en/latest/build/index.html
Thanks
Regards
Kian