How would you create infinite simulation loop in modelsim using erilog/ vhdl

You could just post your homework assignment for us. :)

Hi Jakob,

I presume you are aware of the $stop and $finish directives in verilog?

thanks for your help..

This should make modelsim get stuck in an infinite loop in VHDL:

signal a : std_logic := '1';
signal b : std_logic := '0';
...
b <= a and not b;

thanks tricky... did end up doing something like that. general question can anyone give me an example how do i make 2 always loops to be continuously switching between each other

you can try

Did I conceive a circuit under quartusII and do I want validated it by a file of data to elaborate by a program in C language, and to recover the exits as a file text, how to make?