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Altera_Forum's avatar
Altera_Forum
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10 years ago

how to use set false path properly to constrain clocks in different clock domains

IN my project, I have two different clock domains.One is CLK_In_50MHz from oscillator outside. The other is ADC_CLK,48MHz,which is the DCO output clock of an ADC. Then I generate a pll,named PLL_ADC in my project, which is drived by ADC_CLK. c1 is one output clock of pll,named ADC_CLK_x2. It's frequency is 96MHz.c1 is the main signal processing clock in other entities.

Then I compiled my project, it says that the setup time slack of c1 is negative. I see the worst-case timing paths.I find that the launch clock is CLK_In_50MHz ,and the latch clock is c1. I konw that it this two clocks are considered relative when it compiling. I used set false paths commond in my sdc file. But it didn't work. I don't know whether I use it correctly or not. In my sdc file, i_PLL_ADC|altpll_component|auto_generated|pll|clk[1] is the clock name of c1,which is one output of pll. I don't know whether I can use this name in set false paths commond or not.

My tcl file and worst-case timing paths are attached.

Someone can help me?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    You shouldn't need to use the set_false_path command, the clock groups features should be enough. Timequest isn't supposed to analyse timing between asynchronous clock groups. Try adding the PLL clock in another group.

    I don't remember the exact command but you can ask Timequest to reparse your sdc constraints file. See if you have any warning about ignored commands or clocks not found when it executes your sdc commands.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    derive_pll_clocks command can constrain all pll output clocks. Do I need to add the pll clocks on another group?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    AFAIK derive_pll_clocks doesn't put the derived clocks in any group autmoatically. You have to put all of them in a set_clock_groups command, where all the pll output clocks that are synchronized should be in the same group.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I don't know how to seperate pll clocks in different clock domain by set_clock_groups command.

    Dose set_clock_groups -asynchronous -group {} -group {} command work?

    can you give me an example?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    This is from one of my projects. I give my pll clock names to be able to find them easier afterwards 

    
derive_pll_clocks
set time25_clock    clocks_1|PllTimeInst|altpll_component|auto_generated|pll1|clk
set time62_5_clock  clocks_1|PllTimeInst|altpll_component|auto_generated|pll1|clk
set time10_clock    clocks_1|PllTimeInst|altpll_component|auto_generated|pll1|clk
set time187_5_clock clocks_1|PllTimeInst|altpll_component|auto_generated|pll1|clk
set time50_clock    clocks_1|PllTimeInst|altpll_component|auto_generated|pll1|clk
set spread25_clock  clocks_1|PllSpreadInst|altpll_component|auto_generated|pll1|clk
set spread100_clock clocks_1|PllSpreadInst|altpll_component|auto_generated|pll1|clk
set ssram_clock     clocks_1|PllSpreadInst|altpll_component|auto_generated|pll1|clk
set_clock_groups -asynchronous -group "$time10_clock $time25_clock $time50_clock" -group "$time62_5_clock $time187_5_clock" -group "$spread25_clock $spread100_clock $ssram_clock" -group } ]