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Honored Contributor
Honored Contributorhow to use set false path properly to constrain clocks in different clock domains
IN my project, I have two different clock domains.One is CLK_In_50MHz from oscillator outside. The other is ADC_CLK,48MHz,which is the DCO output clock of an ADC. Then I generate a pll,named PLL_ADC ...
Altera_ForumHonored Contributor
Honored ContributorI don't know how to seperate pll clocks in different clock domain by set_clock_groups command.
Dose set_clock_groups -asynchronous -group {} -group {} command work? can you give me an example?
