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Honored Contributor
Honored Contributorhow to use set false path properly to constrain clocks in different clock domains
IN my project, I have two different clock domains.One is CLK_In_50MHz from oscillator outside. The other is ADC_CLK,48MHz,which is the DCO output clock of an ADC. Then I generate a pll,named PLL_ADC ...
Altera_ForumHonored Contributor
Honored ContributorThis is from one of my projects. I give my pll clock names to be able to find them easier afterwards
derive_pll_clocks
set time25_clock clocks_1|PllTimeInst|altpll_component|auto_generated|pll1|clk
set time62_5_clock clocks_1|PllTimeInst|altpll_component|auto_generated|pll1|clk
set time10_clock clocks_1|PllTimeInst|altpll_component|auto_generated|pll1|clk
set time187_5_clock clocks_1|PllTimeInst|altpll_component|auto_generated|pll1|clk
set time50_clock clocks_1|PllTimeInst|altpll_component|auto_generated|pll1|clk
set spread25_clock clocks_1|PllSpreadInst|altpll_component|auto_generated|pll1|clk
set spread100_clock clocks_1|PllSpreadInst|altpll_component|auto_generated|pll1|clk
set ssram_clock clocks_1|PllSpreadInst|altpll_component|auto_generated|pll1|clk
set_clock_groups -asynchronous -group "$time10_clock $time25_clock $time50_clock" -group "$time62_5_clock $time187_5_clock" -group "$spread25_clock $spread100_clock $ssram_clock" -group } ]
