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Altera_Forum
Honored Contributor
10 years agohow to use set false path properly to constrain clocks in different clock domains
IN my project, I have two different clock domains.One is CLK_In_50MHz from oscillator outside. The other is ADC_CLK,48MHz,which is the DCO output clock of an ADC. Then I generate a pll,named PLL_ADC ...
Altera_Forum
Honored Contributor
10 years agoYou shouldn't need to use the set_false_path command, the clock groups features should be enough. Timequest isn't supposed to analyse timing between asynchronous clock groups. Try adding the PLL clock in another group.
I don't remember the exact command but you can ask Timequest to reparse your sdc constraints file. See if you have any warning about ignored commands or clocks not found when it executes your sdc commands.