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Honored Contributor
Honored Contributorhow to use set false path properly to constrain clocks in different clock domains
IN my project, I have two different clock domains.One is CLK_In_50MHz from oscillator outside. The other is ADC_CLK,48MHz,which is the DCO output clock of an ADC. Then I generate a pll,named PLL_ADC ...
Altera_ForumHonored Contributor
Honored ContributorAFAIK derive_pll_clocks doesn't put the derived clocks in any group autmoatically. You have to put all of them in a set_clock_groups command, where all the pll output clocks that are synchronized should be in the same group.
