How to use SCLR port of an Flip flop in Verilog?

I am using Quartus Prime 17.1 and I am trying to use SCLR port of the flip flop to synchronously reset the flip flop, however it synthesize a mux driven by reset input. My code is:

module ff(clk, q,a,b, reset,ce,asynch_load,data,synch_reset,synch_load);
    input logic clk,a,b,reset,ce,asynch_load,data,synch_reset,synch_load;
    logic d;
    
    output logic q;
    
    assign d = ((((q&a)|b)));
    always @ (negedge reset or posedge asynch_load or posedge clk)
    begin
        // The asynchronous reset signal has highest priority
        if (!reset)
        begin
            q <= 1'b0;
        end
        // Asynchronous load has next priority
        else if (asynch_load)
        begin
            q <= data;
        end
        else
        begin
            // At a clock edge, if asynchronous signals have not taken priority,
            // respond to the appropriate synchronous signal.
            // Check for synchronous reset, then synchronous load.
            // If none of these takes precedence, update the register output 
            // to be the register input.
            if (ce)
            begin
                if (synch_reset)
                begin
                    q <= 1'b0;
                end
                else if (synch_load)
                begin
                    q <= data;
                end
                else
                begin
                    q <= d;
                end
            end
        end
    end
    
endmodule

And here is the RTL of synthesized architecture:

https://alteraforum.com/forum/attachment.php?attachmentid=14868&stc=1

How could I use SCLR input to reset the flip flop value?