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Altera_Forum's avatar
Altera_Forum
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8 years ago

How to use SCLR port of an Flip flop in Verilog?

I am using Quartus Prime 17.1 and I am trying to use SCLR port of the flip flop to synchronously reset the flip flop, however it synthesize a mux driven by reset input. My code is: module ff(cl...
Altera_Forum's avatar
Altera_Forum
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8 years ago

I don't see what the problem is... The synthesized RTL will set the output synchronously to 0 if the synch_reset output is 1, which is the definition of a synchronous reset. The registers in the FPGA don't have a dedicated synchronous reset pin if I'm not mistaken so the behaviour is created with logic around the D synchronous input.

AZahe1's avatar
AZahe1
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5 years ago

isn't the SCLR port in the flip flop shown in the RTL schematic is for the "Synchronous Clear"? and why is it driven to "1'h0"? and what exactly is "1'h0'?