How to use SCLR port of an Flip flop in Verilog?

In this old post, the code is very close to, but not exactly matching the template in Quartus that would use the synchronous reset correctly. I checked the template in the tool in 20.1 and it should be "if (!synch_reset)" instead of "if (synch_reset)" to match the active low synchronous reset of the flip-flop in the device. As such, Quartus generated extra logic to conform with this active high synchronous reset. But then the Design Recommendations user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommendations.pdf) conflicts with that saying sclr is active high and sload is active low! So I'm not sure which combination would lead to direct connections to the flip-flop without extra logic without trying them out (and it might be different between different target devices). "1'h0" is the single bit input into sclr set to 0 to provide the active high sclr functionality specified in the code based on the synch_reset input of the design driving the select line of that mux.

#iwork4intel