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Honored Contributor
Honored ContributorHow to use a module or interface instance in an interface?
Hello,every one!
I have some problem in using interface of SystemVerilog: I have a predefined module and interface, and I want to use them in another interface. The example code of module in interface is:
module predef_mod(
input clk,
input rst,
output reg cntr_o
);
always_ff @(posedge clk)
if (rst) cntr_o <= 4'd0;
else cntr_o <= cntr_o + 4'd1;
endmodule
interface use_predef_mod_if(
input clk,
input rst,
output wire cntr
);
predef_mod modi(
.clk(clk),
.rst(rst),
.cntr_o(cntr)
);
endinterface
interface predef_if(
input clk,
input rst,
output reg cntr_o
);
always_ff @(posedge clk)
if (rst) cntr_o <= 4'd0;
else cntr_o <= cntr_o + 4'd1;
endinterface
interface use_predef_intf_if(
input clk,
input rst,
output wire cntr
);
predef_if ifi(
.clk(clk),
.rst(rst),
.cntr_o(cntr)
);
endinterface
