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Honored Contributor
Honored ContributorHow to use a module or interface instance in an interface?
Hello,every one! I have some problem in using interface of SystemVerilog: I have a predefined module and interface, and I want to use them in another interface. The example code of module in int...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I've noticed that no vendor of FPGAs implements all the features of Verilog/VHDL, at least for the newer versions. Why are features added to languages if the vendors decide not to implement them? Should these language definitions be scaled back to something that all FPGA vendors agree to implement? Are abstraction features from computer science really all that useful for hardware design? --- Quote End --- The features added are now usually for simulation. You'll find Modelsim and Cadence have v good SV and VHDL support. For FPGAs, there isnt a lot you cannot do with existing language features, so the vendors dont see the point in adding more.
