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I've noticed that no vendor of FPGAs implements all the features of Verilog/VHDL, at least for the newer versions. Why are features added to languages if the vendors decide not to implement them? Should these language definitions be scaled back to something that all FPGA vendors agree to implement? Are abstraction features from computer science really all that useful for hardware design?
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The features added are now usually for simulation. You'll find Modelsim and Cadence have v good SV and VHDL support.
For FPGAs, there isnt a lot you cannot do with existing language features, so the vendors dont see the point in adding more.
Honored Contributor
