There are 3 reasons why I think this is the case:
1) SDC and TimeQuest API Reference Manual (this is from Quartus II, I was unable to find this manual for Quartus Prime pro)
Page 2-35
set_max_delay
DescriptionSpecifies a maximum delay exception for a given path.The maximum delay is similar to changing the setup relationship (latching clock edge - launching clock edge), except that it can be applied to input or output ports without input or output delays assigned to them. Maximum delays are always relative to any clock network delays (if the source or destination is a register) or any input or output delays (if the source or destination is a port). Therefore, input delays and clock latencies are added to the data arrival times. Clock latencies also added to data required times and output delays are subtracted from data required times.
In practice:
2) Although applying set_min_timing delay and set_max_timining delay in the timing analyzer does not return any errors or warnings, when performing final timing analysis the paths that I assignd constraints to can not be found. Note: these are still visible in the post P&R netlist!
3) Using signal tap I can observer that no matter how I constrain paths, these paths do not fit the constraint at all. And worse, with each new build the behaviour is different.
I hope this proves my case, can you help me find a solution?
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