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BStui2's avatar
BStui2
Icon for New Contributor rankNew Contributor
5 years ago

How to time constrain an combinational loop on FPGA?

Hi, I am trying to time constrain a combinational loop. I need a free running oscillator which I can coarsly tune and enable. Unfortunately commands like: set_net_delay set_min_delay set_max_de...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
5 years ago

Hi KhaiY,

I was wondering why you ask him an update while said before that quartus does not support it.

Maybe he wen't back to Xilinx

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi AEsqu,

    Just to check with BStui2 if there is any other questions before I transition this thread to community support.

    Since there is no other question, I will transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

    Best regards,

    KhaiY