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BStui2's avatar
BStui2
Icon for New Contributor rankNew Contributor
6 years ago

How to time constrain an combinational loop on FPGA?

Hi, I am trying to time constrain a combinational loop. I need a free running oscillator which I can coarsly tune and enable. Unfortunately commands like: set_net_delay set_min_delay set_max_de...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Upon checking, setting the net delay of a combinational loop is currently unsupported in the software.

Thanks.

Best regards,

KhaiY