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MohdAnnuar_S_Intel's avatar
MohdAnnuar_S_Intel
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6 years ago

How to solve unexpected error in JTAG server -- error code 35?

This is seen on Windows Quartus prime pro version 17.1 programmer via USB Blaster II cable. I am trying to program FPGA on stratix 10 GX development board.

7 Replies

    • MDe_M1's avatar
      MDe_M1
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      5 years ago

      Hi, I have the same problem when i try to program a max10 fpga in a new board developed by the hardware team. I don't how can I change the tck frequency because I am new about tcl scripting. Could you help me to set the right clock using tcl scripting? I have 17.0.0 Build 595 04/25/2017 SJ Lite Edition installed.

      Thanks,

      MDM

  • MohdAnnuar_S_Intel's avatar
    MohdAnnuar_S_Intel
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    6 years ago

    Hi,

    I tried setting the download cable frequency to 6Mz

    PS C:\intelFPGA_pro\17.1\qprogrammer\bin64> .\jtagconfig.exe --setparam 1 JtagClock 6M

    PS C:\intelFPGA_pro\17.1\qprogrammer\bin64> .\jtagconfig.exe

    1) USB-BlasterII [USB-1]

    020A40DD 5M(1270ZF324|2210Z)/EPM2210

    C32150DD !

    Captured DR after reset = (0041481BBC32150DD) [65]

    Captured IR after reset = (0AAC01) [21]

    Captured Bypass after reset = (2) [3]

    Captured Bypass chain = (2) [3]

    JTAG clock speed 6 MHz

    However I still get the code 35 error:

  • ShafiqY_Intel's avatar
    ShafiqY_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hi MSuha1,

    I'm apologize for late reply.

    Here's the comment from my colleague:

    " I found that this "error code 35" was caused to due to a network issue at the customer's end. Turning off the network switch helped to program the board successfully."

    I hope this will help you to move forward.

    Thanks

    • MohdAnnuar_S_Intel's avatar
      MohdAnnuar_S_Intel
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      6 years ago

      Thank you for the follow up. We have tried turning off the network connection but the problem persists. However, we found out that the FPGA chip we have on board is different from our counterpart who generates the FPGA image. They seems to have the Engineering release version while we have the released version.

      • ShafiqY_Intel's avatar
        ShafiqY_Intel
        Icon for Frequent Contributor rankFrequent Contributor
        6 years ago

        Hi MSuha1,

        May I know the status of this issue?

        Thanks