How to simulate a ram in modelsim6.5b along with .mif file

I am using Altera-Modelsim starter edition. And My design files are in verilog, but the altera_mf library has .vhdl file, particularly, altera_mf.vhd.

Can we have different design files in different HDL languages and still simulate in starter edition verion of modelsim?

Thanks and regards,

Kapil

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Hi,

I generated a ram verilog moudle using the megafunction wizard. I also generated a .mif file using QUARTUS. I filled .mif file with decimal numbers; just want to confirm if it is the correct way to fill .mif file?

Now I instantiated ram file in my design and tried to simulate the design using Altera-modelsim. I am getting following error:

Unresolved reference to 'altsyncram_component' in altsyncram_component.clock_enable_input_a.

and some more errors ofthis type.

I am using following command to simulate my design:

vsim -L altera_mf -t ns work.clkgen_top_tb

Wouldyou please tell me what is the potential issue? ALso, how do we simulate the design in modelsim with ram initialized using .mif file?

Thanks and regards,

Kapil

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Hi,

1. ModelSim-AE (free or paid) does not support simulation of mixed (Verilod + VHDL) designs

2. ModelSim does not, AFAIK, support Altera's .MIF files. You'll need to convert them to ModelSim memory files.

Alternatively, you can also use .HEX files which are supported by both Quartus and ModelSim.

I thank you very much for the reply.

I am very sorry for long writeup here, but I would sincerely request you to consider the length of the email commensurate to my earnest efforts.

1)

So, what is way you suggest me to proceed? When I try to simulate the design using Quartus 9.1 internal simulator, I get a pop window saying that "Altera recommends using modelsim-altera for all the simulations". And since you are saying that modelsim-altera does not support mixed designs. How do I handle this dilemma? Is rewriting my design in VHDL the only solution? But in that case, I am doubtful that what if some of libraries be in verilog?

2) Regarding memory initialization, I have following things to say:

Is it possible to initialize a custom memory (I will write a code for that) in Quartus. I am thinking of following steps: I will create a design in verilog along with memory. and I will simulate it with memory using $resdmemb type commands. Then I will bring the whole design in Quartus and generate the sof file for FPGA (cyclone III). I hope that the synthesis tool inside Quartus will recognize the memory instantiation and will implement it using an embedded memory block.

But my doubt here is that: how will I initialize the custom embedded memory inside FPGA?

I tried to write a .mif file with the data filled in decimal format but it did not seem to work properly. Would you please tell me if that is the correct way to fill a .mif file?

I also tried to create a .hex file, but it did not allow me write a hex number in it. I was not able to fill the content of memory with A, B, ..E. I was only able to write data using 0-9 numerals. Would you please tell me how to fill the .hex file?

I once again apologize for the long email. I appreciate your kind replies.

Thanks and regards,

Kapil

Hi,

1. You can use ModelSim-AE to simulate either Verilog or VHDL. No need to rewrite your design to VHDL. There are both Verilog and VHDL versions of the Altera libraries. I think you're having some issue with libraries and ModelSim-AE is somehow is trying to load VHDL libraries instead of the Verilog libraries.

But I can't tell what's wrong.

2. Quartus (latest versions at least) also understantds $readmemb and $readmemh and will initialize the RAM contents properly.

.HEX files (Intel HEX format) do not have a straightforward format and are not very suitable for manual editing.

Thanks for the reply.

I think you may be right that the simulator is picking .vhd version of libraries. If that is the case, then how do I set the library files to verilog files. Where are these files located in installation hierarchy?

Actually, the error I am getting during simulation does not exactly say like that. The error I am getting is as following:

Unresolved reference to 'altsyncram_component' in altsyncram_component.clock_enable_input_a

Here 'altsyncram_component' is the name of the instance inside the single-port ram I generated using megafunction and clock_enable_input_a is a parameter of that instance.

I do not know how to get away with above error ( i.e. the error related to unresolved reference)

Thanks and Best Regards,

Kapil

Thanks for the replies.

I am able to resolve the library issue by picking the verilog libraries located in altera_mf_ver directory.

I appreciate your kind replies.

-Kapil