How to simulate a ram in modelsim6.5b along with .mif file

Hi,

1. You can use ModelSim-AE to simulate either Verilog or VHDL. No need to rewrite your design to VHDL. There are both Verilog and VHDL versions of the Altera libraries. I think you're having some issue with libraries and ModelSim-AE is somehow is trying to load VHDL libraries instead of the Verilog libraries.

But I can't tell what's wrong.

2. Quartus (latest versions at least) also understantds $readmemb and $readmemh and will initialize the RAM contents properly.

.HEX files (Intel HEX format) do not have a straightforward format and are not very suitable for manual editing.