How to simulate a ram in modelsim6.5b along with .mif file

I am using Altera-Modelsim starter edition. And My design files are in verilog, but the altera_mf library has .vhdl file, particularly, altera_mf.vhd.

Can we have different design files in different HDL languages and still simulate in starter edition verion of modelsim?

Thanks and regards,

Kapil

--- Quote Start ---

Hi,

I generated a ram verilog moudle using the megafunction wizard. I also generated a .mif file using QUARTUS. I filled .mif file with decimal numbers; just want to confirm if it is the correct way to fill .mif file?

Now I instantiated ram file in my design and tried to simulate the design using Altera-modelsim. I am getting following error:

Unresolved reference to 'altsyncram_component' in altsyncram_component.clock_enable_input_a.

and some more errors ofthis type.

I am using following command to simulate my design:

vsim -L altera_mf -t ns work.clkgen_top_tb

Wouldyou please tell me what is the potential issue? ALso, how do we simulate the design in modelsim with ram initialized using .mif file?

Thanks and regards,

Kapil

--- Quote End ---