How to simulate a ram in modelsim6.5b along with .mif file

Thanks for the reply.

I think you may be right that the simulator is picking .vhd version of libraries. If that is the case, then how do I set the library files to verilog files. Where are these files located in installation hierarchy?

Actually, the error I am getting during simulation does not exactly say like that. The error I am getting is as following:

Unresolved reference to 'altsyncram_component' in altsyncram_component.clock_enable_input_a

Here 'altsyncram_component' is the name of the instance inside the single-port ram I generated using megafunction and clock_enable_input_a is a parameter of that instance.

I do not know how to get away with above error ( i.e. the error related to unresolved reference)

Thanks and Best Regards,

Kapil