How to prevent conversion to "equivalent circuits with latches"

Hi everyone... I'm currently working on a Rijndael (AES) Decryptor using the Stratix III family and trying to add a Key check when the Load signal is set to prevent RoundKey re-generation if the Key hasn't changed. However, every attempt I've been making has been incurring conversion to "equivalent circuits with latches" on Quartus II.

Below is the related Code... Removing the if(RoundKey[0] == Key) sections compiles just fine but there will no longer be a Key Check. Is there any way to fix this without adding a LoadKey input?

Your help is greatly appreciated.

// Check Status of Key Generation,

assign Done_Keys = |RoundKey[10][0:15];

// Store RoundKeys

always @ (posedge clk or posedge Load)

begin

if( Load )

begin

if( RoundKey[0] == Key )

// Better way to implement this part?

RoundKey[10] <= RoundKey[10];

else

RoundKey[10] <= {128{1'b0}};

end

else if( !Done_Keys )

RoundKey[Round] <= RoundKey_New;

end

// Updates Round Counter

always @ (posedge clk or posedge Load or posedge Reset or posedge Done_Keys)

begin

if( Reset )

Round <= 4'hx;

else if( Load )

// Initialize Round Counter

begin

if( RoundKey[0] == Key )

Round <= 4'hb;

else

Round <= 4'h0;

end

else

// Update Round

Round <= (Done_Keys) ? Round - 4'h1 : Round + 4'h1;

end

FYI: For those that do not know AES, a key is taken and 10 additional RoundKeys are generated. ie RoundKey[0] = Key and RoundKey[1 thru 10] are the generated ones. To Encrypt, you use the RoundKeys in order (0 to 10). To Decrypt, you use them in reverse order.

Since it takes one cycle to generate each key and 10 cycles for decryption, the Key Check can potentially cut the time in half.