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Altera_Forum
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17 years ago

How to prevent conversion to "equivalent circuits with latches"

Hi everyone... I'm currently working on a Rijndael (AES) Decryptor using the Stratix III family and trying to add a Key check when the Load signal is set to prevent RoundKey re-generation if the Key ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The original design was actually Synchronous Load but I decided to convert it to async load and output to decrease processing by an average of 10% for Encryption and 5% for Decryption.

When I think about it more... I may have misunderstood the idea of asynchronism. If the loading occurs close to a rising edge, initialization won't have enough time to process and throw everything off...

If there's enough time, I'll try to convert it back to Synchronous.