How to prevent conversion to "equivalent circuits with latches"

I wanted to add an asynchronous Load "feature" hence the second input.

Without the Key Check functionality (basically remove the if( RoundKey[0] sections), everything compiles on on Quartus II for the Stratix III but I guess synthesis and proper functionality are two different things.

I just learned Verilog as a final project for University and I'm not really a hardware guy to start with (background mostly in software and power) so pardon my limited knowledge. It is due in a week so I'll probably fiddle with it for another 2-3 days then concentrate on the report.