How to prevent conversion to "equivalent circuits with latches"

The problem is caused by your overall design structure. The expression

--- Quote Start ---

always @ (posedge clk or posedge Load)

begin

if( Load )

--- Quote End ---

would require flip-flops with asynchronous load input for an exact implementation. It's one thing, that Verilog syntax allows multiple clock sensitive conditions in an always block, but another, if these constructs are synthesizable. They are fine in simulation, of course.

Hopefully, it can be changed to a true synchronous design with a clock and multiple enable signals (and possibly an asynchronous reset). As is, it's not synthesizable with most newer Altera FPGA, I think.

P.S.: It should be considered, that asynchronous conditions, that override the synchronous action, apart from having no adequate hardware in many FPGA, are susceptible for timing problems and can effectively a prevent a reliable timing analysis.