How to Instantiate PLL and Reset without using QSYS or Platform designer

Question

I have relatively simple design using logic only,  no SOC or NIOS or hard processor.  I need to Instantiate the internal PLL and Reset monitor, can I do this manually or do I need to use Platform designer.   Likewise I can not find the documentation on how to set / place / use I/O blocks at the pin.   I need to have an I2C controller with bidirectional I/O pin.   does the tool automatically place things to I/O logic cells based on design constraints, or do I have to manually do this?

sstrell · Answer

In the main Quartus Prime software, you access IP, like a PLL, from the IP Catalog.  You generate the IP, which includes instantiation templates which simplifies instantiating the IP into your HDL code.
As for I/O, after performing at least Analysis &amp; Elaboration (first stage of synthesis), you can open the Pin Planner from the Assignments menu to make I/O assignments.

jsly · Answer

Thanks, I have Prime Lite and when I click on IPCatalog it does nothing?

sstrell · Answer

There should be a list of all the IP you can add to your design.  If not, you may have a bad installation of the software.

jsly · Answer

Yes I see a very small window open with very limited IP.    There is no IP for connection to Global Reset.    where is the documentation for the device level instantiation,  you know the stuff that used to be called "Primitives"    the old Altera specific general purpose IP that you can manually instantiate.     like clock buffers, and I/O cells, and Global Device Reset, and the like,   or am I supposed to somehow get the tool to do all this for me using the platform designer,  which seems total over kill to create a system with nothing but a reset circuit and a clock buffer.    I  found and am using the PLL

jsly · Answer

I am using a max 10 fpag,  with external pin DEV_CLRn is disabled in prime tool and there is no external pullup or pulldown, so how do I attach to the DEV_CLRn signal,  is this signal internally generated inside the device, or will it get synthesized out because the tool setting has the pin disabled on the Max10-&gt;Device-&gt;Device and Pin Options-&gt;General-&gt; unchecked "Enable device - wide reset (DEV_CLRn) is unchecked.       how does the device come out of reset, do i still have an internal device_reset signal generated by an internal RC type circuit?  IF so how do I instantiate or connect to that signal???

Forum Discussion

How to Instantiate PLL and Reset without using QSYS or Platform designer

9 Replies

Recent Discussions

AGI027 Dev Kit example build takes a long time

Warning at Standard 25.1 by Arria 10

Perpetual license Quartus II doesn't allow to build Cyclone V devices anymore.

Quartus Eda_Writer keeps crashing

Failing IO buffer