New Contributor
New ContributorYes I see a very small window open with very limited IP. There is no IP for connection to Global Reset. where is the documentation for the device level instantiation, you know the stuff that used to be called "Primitives" the old Altera specific general purpose IP that you can manually instantiate. like clock buffers, and I/O cells, and Global Device Reset, and the like, or am I supposed to somehow get the tool to do all this for me using the platform designer, which seems total over kill to create a system with nothing but a reset circuit and a clock buffer. I found and am using the PLL
Super ContributorI'm not quite sure what you are referring to. Are you thinking about what you would add in a schematic design? The clock control block IP is essentially a clock buffer, and I/O cells are not manually added to a design as an IP other than in a schematic (and you would still need to go to the Pin Planner to create I/O assignments). And I've never heard of a global device reset IP.
If you're creating an HDL design (not using Platform Designer), you create a top-level design in Verilog, SystemVerilog, or VHDL. You can create IP from the IP catalog and then instantiate that IP in your HDL code using the instantiation template generated by the IP Parameter Editor.
