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JSLY's avatar
JSLY
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4 years ago

How to Instantiate PLL and Reset without using QSYS or Platform designer

I have relatively simple design using logic only, no SOC or NIOS or hard processor. I need to Instantiate the internal PLL and Reset monitor, can I do this manually or do I need to use Platform des...
sstrell's avatar
sstrell
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4 years ago

There should be a list of all the IP you can add to your design. If not, you may have a bad installation of the software.

JSLY's avatar
JSLY
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4 years ago

I am using a max 10 fpag, with external pin DEV_CLRn is disabled in prime tool and there is no external pullup or pulldown, so how do I attach to the DEV_CLRn signal, is this signal internally generated inside the device, or will it get synthesized out because the tool setting has the pin disabled on the Max10->Device->Device and Pin Options->General-> unchecked "Enable device - wide reset (DEV_CLRn) is unchecked. how does the device come out of reset, do i still have an internal device_reset signal generated by an internal RC type circuit? IF so how do I instantiate or connect to that signal???