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JSLY's avatar
JSLY
Icon for New Contributor rankNew Contributor
4 years ago

How to Instantiate PLL and Reset without using QSYS or Platform designer

I have relatively simple design using logic only, no SOC or NIOS or hard processor. I need to Instantiate the internal PLL and Reset monitor, can I do this manually or do I need to use Platform des...
Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

I am Farabi who will be supporting this request.

As Sstrell mentioned, If you're creating an HDL design (not using Platform Designer), you create a top-level design in Verilog, SystemVerilog, or VHDL. You can create IP from the IP catalog and then instantiate that IP in your HDL code using the instantiation template generated by the IP Parameter Editor.

Dev_CLRn pin is an external pin which supposed to be controlled by external IO or some other microcontrollers. It can't be controlled from inside the FPGA. So in top level schematic, this pin will be connected to external IOs.

regards,
Farabi