Occasional ContributorHow to instantiate components of Cyclone V IOE for design.
Hello,
I am trying to instantiate the DDR and read FIFO items that are integrated into the Cyclone V I/O elements (IOEs). I know you can instantiate DDR registers using the ALTDDIO IP. However, I have not been able to find any way to instantiate the READ FIFO that is attached to the output of the DDR registers. How can I instantiate the Read FIFO?
This is an image from the Cyclone V's Volume 1 User Guide: Device Integration and Interfaces. you can see at the bottom is the DDR registers and attached to the output is a block labeled "Read FIFO".
Thank you,
Tucker Z
Structures like that are usually added as needed based on the design. If you add a FIFO IP and connect it to an I/O or use an IP that has a parameter for using the FIFO, the synthesized design would make use of that hardware. There's no specific IP as far as I know to implement that particular FIFO.
