Forum Discussion
TuckerZ
Occasional Contributor
Occasional ContributorHow to instantiate components of Cyclone V IOE for design.
Hello, I am trying to instantiate the DDR and read FIFO items that are integrated into the Cyclone V I/O elements (IOEs). I know you can instantiate DDR registers using the ALTDDIO IP. However, I h...
Structures like that are usually added as needed based on the design. If you add a FIFO IP and connect it to an I/O or use an IP that has a parameter for using the FIFO, the synthesized design would make use of that hardware. There's no specific IP as far as I know to implement that particular FIFO.
SyafieqS
Super Contributor
Super ContributorHi Tucker,
This is true as mentioned by sstrell. In this case place and route engine will automatically choose the resources needed to implement a design. But to implement the fifo read to output of DDR, I am checking if that is possible or not by manually instantiating it.
