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TuckerZ
Occasional Contributor
Occasional ContributorHow to instantiate components of Cyclone V IOE for design.
Hello, I am trying to instantiate the DDR and read FIFO items that are integrated into the Cyclone V I/O elements (IOEs). I know you can instantiate DDR registers using the ALTDDIO IP. However, I h...
Structures like that are usually added as needed based on the design. If you add a FIFO IP and connect it to an I/O or use an IP that has a parameter for using the FIFO, the synthesized design would make use of that hardware. There's no specific IP as far as I know to implement that particular FIFO.
SyafieqS
Super Contributor
Super ContributorHi Tucker,
There is step to infer fifo manually that might be help for you design to link at ddr output.
You may look at below documents.
