Honored ContributorI have a verilog project,and already run and got my .vo file,now someone else want to write a VHDL testbench for my project to implement a whole scheduling emulation,how?
ie: my verilog module name is im1,if i write COMPONENT im1 PORT ( XXXX:XXXXXX ); end COMPONENT; in VHDL testbench,i get error message: im1_tb.vhd(38): Instantiation of 'im1' failed.
Honored ContributorWhat tool are you compiling and simulating your code in?
Have you compiled the verilog before the VHDL which instantiates it?Honored Contributorthe tool I compile my verilog file is QUARTUS 9.0,so actually i can get my .vo file for timing simulation...
Honored Contributoryou can't use a VHDL testbench with Quartus II Simulator and you can't do mixed language simulations with the ModelSim-Altera Edition.
Honored ContributorOf course,the VHDL testbench is only written for Modelsim.
The testbench is only implemented to generate the input signal and get the output result,so I think it must be the same if vary from VHDL and verlog (etc) , in ModelSim-Altera Edition I can't use a VHDL testbench for a verilog vo file?what about SE edition?Honored Contributorin ModelSim-Altera Edition I can't use a VHDL testbench for a verilog vo file?what about SE edition?Mixed language has been a separate licence, also with SE, as far as I know. But you simply can try, ModelSim will surely tell, if it don't like the simulation setup.
Honored Contributorthanks,I got it.
