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Altera_Forum
Honored Contributor
Honored Contributorhow to implement a VHDL testbench for verilog module?
I have a verilog project,and already run and got my .vo file,now someone else want to write a VHDL testbench for my project to implement a whole scheduling emulation,how? ie: my verilog module nam...
Altera_ForumHonored Contributor
Honored ContributorOf course,the VHDL testbench is only written for Modelsim.
The testbench is only implemented to generate the input signal and get the output result,so I think it must be the same if vary from VHDL and verlog (etc) , in ModelSim-Altera Edition I can't use a VHDL testbench for a verilog vo file?what about SE edition?
