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Altera_Forum's avatar
Altera_Forum
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16 years ago

how to implement a VHDL testbench for verilog module?

I have a verilog project,and already run and got my .vo file,now someone else want to write a VHDL testbench for my project to implement a whole scheduling emulation,how? ie: my verilog module nam...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Of course,the VHDL testbench is only written for Modelsim.

The testbench is only implemented to generate the input signal and get the output result,so I think it must be the same if vary from VHDL and verlog (etc) , in ModelSim-Altera Edition I can't use a VHDL testbench for a verilog vo file?what about SE edition?