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Honored Contributor
Honored Contributorhow to implement a VHDL testbench for verilog module?
I have a verilog project,and already run and got my .vo file,now someone else want to write a VHDL testbench for my project to implement a whole scheduling emulation,how? ie: my verilog module nam...
Altera_ForumHonored Contributor
Honored Contributorthe tool I compile my verilog file is QUARTUS 9.0,so actually i can get my .vo file for timing simulation...
