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Altera_Forum
Honored Contributor
Honored Contributorhow to implement a VHDL testbench for verilog module?
I have a verilog project,and already run and got my .vo file,now someone else want to write a VHDL testbench for my project to implement a whole scheduling emulation,how? ie: my verilog module nam...
Altera_ForumHonored Contributor
Honored ContributorMixed language has been a separate licence, also with SE, as far as I know. But you simply can try, ModelSim will surely tell, if it don't like the simulation setup.
